AMD Trinity Architectural Preview - Part IV

APU architecture detailed in depth right before the launch

Besides an enhanced IPC and generally, a more capable x86 core architecture, AMD is shooting for higher frequency on the desktop side and less power consumption in the mobile area. But all these don’t mean that AMD sees any advantage in a low yield 4.5 GHz part on 28 nm SOI rather than having a high yield 3.8 GHz APU on the bulk process.

We found out earlier this year, straight from the mouth of AMD’s Senior VP and CFO Thomas Seifert, under the guidance of newly appointed CEO Rory Read, that AMD would use bulk process for the 28 nm manufacturing step.

“So with respect to SOI (Silicon On Insulator), we made statements that on 28-nanometer, all of our products will be bulk,” said Mr. Seifert during the conference call regarding the Wafer Supply Agreement (WSA) amendment covering 2012.

“We said that at the 28nm node we are going to be on bulk silicon across all products, not only graphics but also CPUs. And we have made no statement beyond that. But for 28 we will be on bulk for all products,” he added.

This is a surprising piece of information coming from a company that has based all their designs on the SOI concept since way back in 2003.

SOI reduces leakage, power consumption and increases the achievable clock frequency.

Why would AMD give up on SOI right now? Well, there are many arguments in the favor of such a move.

First of all would be the fact that AMD was historically a very slow-moving company and Rory Read wants that to change.

He comes from a fast-moving field, such as the PC and laptop market at Lenovo and there, if you happen to have an unsuccessful product, you don’t really have to stay behind your competition too much.

You simply develop a faster product with whatever components you’re dealing with.

This is what Mr. Read seems to want to impose at AMD.

Enough with the long development cycles, enough with the late tape-outs and yield worries. AMD doesn’t have its own FABs anymore, so they can go to whatever foundry they like.

This improves the manufacturing cost scenario quite a bit as, if GlobalFoundries has process and yield problems, AMD can easily go to another foundry.

If one FAB wants to charge them too much, AMD will bid for another’s FAB manufacturing capacities.

When designing a complex architecture such as a new CPU or GPU, you definitely must tailor your design for the foundry you’re in a contract with.

Moreover, if you’re using SOI technology, you must pay IBM to use SOI and then go to a foundry that has an SOI process available and also you must use SOI wafers. When the FABs belonged to AMD, all these conditions were met by its own FABs as it was AMD’s decision which way to go.

Now that AMD doesn’t own any FAB, if they built SOI chips, they’d have to limit themselves to SOI FABs.

Since AMD is already using bulk process at TSMC for their Brazos platform, they’ve seen how advantageous it is to have a design for bulk silicon. If one Fab increases the price, you can take your design to another FAB.

AMD is unhappy they couldn’t do this with their Llano CPUs also. These were made at GlobalFoundries using their SOI 32nm technology. SOI did indeed help as these were much bigger CPUs than AMD’s Zacate and they were running at much higher frequencies than the Brazos chips.

Sure the Brazos family was made, and still is, in TSMC’s bulk 40 nm process, but AMD sees in this the advantage of not being “SOI only.” That’s exactly why they’re going for bulk 28 nm production at GlobalFoundires.

They want to be able to switch foundries if ever necessary and also to have TSMC as backup if a higher quantity is needed. Llano and Brazos were very successful. They’ve represented the fastest CPU ramp in the company’s history.

We believe AMD’s Trinity will double the success of Llano.

AMD knows this and also knows it needs volume. If the new Trinity design is based on the bulk process, or if they have a 32 nm SOI Trinity version and a 28 nm bulk version, AMD will have TSMC as backup if higher quantity is needed.

That is a big “if”. Logically, AMD should not have two different designs for the Trinity architecture; at least not this early. Normally, the 28nm product should already be Trinity’s successor.

Rory Read made it clear that the move toward the bulk process is only a single step and it is happening now because most APUs sell in very big volumes and AMD needs to make them as cheap as possible and, if needed, they’ll use two different foundries for more capacity.

Beyond 28 nm, GlobalFoundries will keep developing on SOI technology and the 28 nm bulk process is actually an advantage for them, as most clients do not design chips for SOI and don’t even need such high frequencies.

AMD will also explore SOI again once they get to a new architecture that would probably benefit from the increased frequency and decreased power consumption that SOI offers and won’t need such high volumes. An example of such an occasion from AMD is the next “Steamroller” based desktop and server CPUs.

For now, Trinity is still 32 nm SOI, just like the succesful Llano.

Only by applying new technologies like Cyclos' clock mesh along with a more mature 32 nm design, AMD managed to get an almost 31% frequency improvement for the new APU.

Moreover, you can get more out of basically the same architecture by developing new and highly applicable features.

This is exactly what AMD does with Brazos 2.0. The APU is built on the same 40 nm process , albeit in a more mature stage, but the platform will appeal to the customers by the means of adding clear practical features to benefit the user.

Considering that the 10% more performance they get from moving to the Piledriver architecture is not that impressive and that the frequency increase only yields in less than 25% performance improvement, AMD added lots of new features to Trinity so that the new APU will uniquely appeal to the future customers.

More on Trinity's new features in Part V of our AMD Trinity Architectural Preview.


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