14 DAY TRIAL // In the first half of 2012, AMD will introduce its next-generation Fusion processors based on the Trinity architecture, and a recently leaked presentation slide has now come out to show us some of the new features that this APU will bring into the market.
The AMD document was uncovered by Donanim Haber and takes a look at the chip maker's Virgo platform and the Trinity APU.
As many of you know, Trinity is built around AMD's second generation of the Bulldozer core which is said to offer a 20% increase in performance over the current Llano architecture, while also bringing a series of new features into view.
These include support for th AVX and AES-NI instruction sets as well as the third version of AMD's Turbo Core technology that automatically adjusts the core speed depending on the number of threads run by the processor.
Much like in the case of Llano, the Trinity APUs will lack any sort of L3 cache memory as AMD wanted to save die space for the integrated Radeon GPU, but it does feature 1MB of Level 2 cache per core.
Since there can be as many as four computing cores in a Trinity APU, the chip tops out at 4MB of L2 cache memory.
In addition to the the switch to Piledriver, AMD also operated a few changes to the integrated memory controller that was now updated to feature support for DDR3-2133 memory and energy-efficient DIMMs that work with 1.25V.
The increased bandwidth available from the memory controller should have an important impact on the performance of the on-die GPU as Llano APUs see a great benefit when coupled together with fast DDR3-1866 DIMMs.
Speaking of the integrated graphics core, the document claims that this can deliver 30% better performance than Llano, while also coming with a new Video Compression Engine and support for AMD's EyeFinity technology.
The first Trinity APUs are expected to arrive in late Q1 or early Q2 2012, as the chips will enter mass production in January of next year. AMD has already sent out engineering samples of these chips to its partners.
