AMD Piledriver CPUs Reach over 4GHz Due to Resonant Clock Mesh

The technology accelerates clocks or cuts power draw without affecting the TDP

By Sebastian Pop on February 23rd, 2012 08:31 GMT
The Piledriver micro-architecture is one of AMD's two main projects for the consumer market, alongside Pitcairn, and it looks like the company has finally unveiled some more things about it.

Advanced Micro Devices is at the International Solid-State Circuits Conference (ISSCC), taking place between February 20 and 24, 2012 in San Francisco, California.

There, it is speaking about its technologies and products, both present and future.

The Piledriver micro-architecture is one of the subjects it has already discussed, even going into detail about the way it will behave.

Apparently, the central processing units (CPUs) based on it will possess a so-called “resonant clock mesh” technology invented by Cyclos Semiconductor.

Through it, the CPUs will know when and how to boost clock speeds by 10% or reduce power consumption by the same percentage without affecting the TDP (thermal design power).

“Now that the Cyclos technology is validated, we’re looking forward to expand into SoC designs via the design automation tools that are in development at Cyclos,” said Marios Papaefthymiou, founder and president of Cyclos Semiconductor.

“We believe resonant clock mesh design will be a key enabler for GHz+ embedded processor IP blocks in next generation SoCs that also require ultra-low power consumption.”

AMD expects Piledriver chips, constructed with the 32nm process, to attain clock frequencies of 4 GHz (and higher) while reducing clock distribution power by up to 24%.

For those who want to know how the technology works, the resonant clock mesh uses on-chip inductors to create an electric pendulum (“tank circuit”) that takes advantage of the ability of the Cyclos inductors and clock control circuits to “recycle: clock power instead of dissipating it on every clock cycle.

“We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule,” said Samuel Naffziger, corporate fellow at AMD.

“Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs.”
AMD Cyclos clock tree
   AMD Cyclos clock tree
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