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June 15th, 2011, 06:30 GMT · By

AMD Officially Details Future Plans for Fusion

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AMD reveals plans for future APUs
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Just about a day ago, Advanced Micro Devices formally launched its newest series of APUs, the A-Series, otherwise known as Llano, for the mainstream market, and it seems that the outfit also has big plans ahead for the Fusion technology.

The A-Series of APUs (accelerated processing units), with mainstream processing and graphics, is just the latest batch of Fusion chips from AMD.

Advanced Micro Devices has been selling such processors since January, all of them with DirectX 11 integrated graphics.

Among their advantages are a lower power draw, faster flow of data between the CPU and GPU (through shared memory) and the ability of the GPU to work as both a graphics engine and application accelerator.

That said, APUs have turned out to be quite appealing to OEMs, this being one of the reasons the Sunnyvale, California-based CPU and GPU maker wants to get Fusion to evolve until the two parts of the chips can be treated as a unified processing element by software programmers.

Among other things, C++ support is planned, unified memory address space (and fully coherent memory) and user-mode scheduling for lower latency task dispatch between the CPU and GPU.

In other words, the Fusion System Architecture (FSA) will get enhancements enabled by the OpenCL and DirectCompute interfaces, leading to both higher performance and higher energy efficiency.

“The first APUs from AMD dramatically increase processing performance while consuming less power and now we are building upon that achievement with our next generation of products” said Phil Rogers, AMD Corporate Fellow.

“Future innovations are intended to make the different processor cores more transparent to programmers. They can then seamlessly tap into the gigaflops of power-efficient performance available on the APU and design even faster, more visually stunning applications on a wide range of form factors.”

Soon, AMD will publish a detailed specification on the features and functionality needed to meet the requirements of the architecture.
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