Memory

AMD Goes for a New High Performance Architecture

The G3MX revealed

By Alexandru Pancescu, Hardware Editor

24th of August 2007, 06:57 GMT

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On server systems that are based on x86 compliant hardware, one of the current performance bottlenecks is represented by the small and clogged data pathways between processor or processors and system memory or RAM. Well, Intel developed its very own technology in an attempt to address this issue and gain a few more percents of data bandwidth that can be put to good use by the processor. The Intel technology is called FB-DIMM from Fully Buffered DIMM and it is specially designed for use in high performance servers and workstations. The FB-DIMM is able to deliver a high data output but its energy scaling and power saving features are underdeveloped as Intel focused almost entirely on the performance issues and neglected the energy efficiency

side.

A short time after Intel presented its FB-DIMM technology, AMD announced that it is working with several other computer hardware manufacturing companies in order to develop a similar technology that will include advanced power saving features too. AMD's solution is called G3MX and according to the news site hothardware, the producing company named this emerging technology the "future Opteron Platform" as the supporting platform is based on a future CPU named Hydra. Hydras will still include an on-die memory controller, as this feature gives then some performance boosts, but unlike current controllers that one will be modified in order to handle DDR3 memory. The main idea is that every Hydra class processor will have its internal memory controller extended by one or more G3MX chips that will in turn connect to the system memory ports. The G3MX chips will provide in fact a serial link to the RAM and the signaling and data flow between the on die memory controller and the extension chips will be based on the HyperTransport 3.0 standard.

As most transactions between processors and system memory are in fact read commands, the link between the memory controllers and the G3MX chips will be asymmetrical and it will work at a higher clock frequency than the memory. Most information suggests that every Hydra processor will support up to four G3MX chips so the processor's internal architecture is very likely to be a native quad core design. Another good feature of the G3MX design is that the chip will support both buffered and the cheaper unbuffered memory that is more readily available and draws less power. It is very likely that the chips will also offer native support for higher speed memory modules like the DDR3-1600 one.

G3MX chips should make their way to hardware manufacturers as engineering samples by the end of the year and the full production is scheduled to start during the fourth quarter of 2008 after some months of market acceptance testing. Some information points to the fact that Intel may be interested in a similar design, currently looking in a buffer on-board implementation for system memory, that will most probably by named AMB2. Still, there is no announced time line for the Intel product, nor is there enough information available at this time.

TAGS:

AMD | G3MX | memory | server | Intel

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