AMD Bulldozer Opteron Processors Will Feature Adjustable TDP

  AMD Opteron 6100 series server processor
AMD's next-generation Opteron server processors, that are based on the Bulldozer architecture, will feature an user adjustable maximum TDP (thermal design power), which will enable clients to set the power consumption of the CPU according to their specific needs.

AMD's next-generation Opteron server processors, that are based on the Bulldozer architecture, will feature an user adjustable maximum TDP (thermal design power), which will enable clients to set the power consumption of the CPU according to their specific needs.

Current Opteron processors rely on turning off P-states in order to obtain a similar result, but this approach limits the maximum operating frequencies of the CPU and can have an detrimental effect on the chip's performance.

“With today’s AMD Power Cap Manager, you can limit the processor P-states and cut power consumption although this limits the processor’s ability to get to the top frequency (which is also the most power-hungry spot on the curve as you can imagine…).”

“By essentially “locking out” the top P-state, the processor never gets into that state, even under heavy utilization, helping cut down total power to the processor,” explains John Fruehe, director of Product Marketing for Server, Embedded and FireStream products at AMD, in a post on the company's official blog.

In order to overcome the performance loss that is associated with disabling P-states, AMD's next-generation Opteron processors based on the Bulldozer architecture will use new TDP Power Cap, according to Fruehe.

Unlike the previous iteration of the technology, this new version will allow customers to set TDP power limits in 1 Watt increments meaning that instead of having to choose between different power draw ratings for processors, one can actually get the CPU to the TDP required.

More importantly, when the workload run doesn't exceed the new modulated power limit, the chip can still operate at its top speed since none of the CPU's P-states are locked.

According to Freuhe, this new technology will be included in both the Valencia and Interlagos cores, which are expected to become official in the third quarter of 2011.

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